In today's fast advancing of technology for semiconductor manufacturing, integration levels are increasing, device features are reduced, and greater demands are increasing for device performance.
As a semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from fabrication issues have also appeared.
In a fabrication process, a chemical mechanical planarizing (CMP) is used to polish a surface of a semiconductive structure. However, CMP process will induce dishing on the surface and complicate a manufacturing process.